Rate match fifo, Rate match fifo -15 – Altera Transceiver PHY IP Core User Manual

Page 498

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Parameter

Range

Description

Enable TX 8B/10B disparity

control

On/Off

When you turn this option On, the PCS includes

disparity control for the 8B/10B encoder. You

force the disparity of the 8B/10B encoder using

the

tx_forcedisp

and

tx_dispval

control

signal.

Enable RX 8B/10B decoder

On/Off

When you turn this option On, the PCS includes

the 8B/10B decoder.

Related Information

Transceiver Architecture in Cyclone V Devices

Rate Match FIFO

The rate match FIFO compensates for the very small frequency differences between the local system clock

and the RX recovered clock.
For more information refer to the Rate Match FIFO sections in the Transceiver Architecture in Cyclone V

Devices.

Table 15-12: Rate Match FIFO Parameters

Parameter

Range

Description

Enable RX rate match FIFO

On/Off

When you turn this option On,

the PCS includes a FIFO to

compensate for the very small

frequency differences between

the local system clock and the

RX recovered clock.

RX rate match insert/delete +ve

pattern (hex)

User-specified 20 bit pattern

Specifies the +ve (positive)

disparity value for the RX rate

match FIFO as a hexadecimal

string.

RX rate match insert/delete -ve

pattern (hex)

User-specified 20 bit pattern

Specifies the -ve (negative)

disparity value for the RX rate

match FIFO as a hexadecimal

string.

When you enable the simplified data interface and enable the rate match FIFO status ports, the rate match

FIFO bits map to the high-order bits of the data bus as listed in the following table. This table uses the

following definitions:
• Basic double width: The Standard PCS protocol mode GUI option is set to basic. The FPGA data

width is twice the PCS data width to allow the fabric to run at half the PCS frequency.

• Serial

TM

RapidIO double width: You are implementing the Serial RapidIO protocol. The FPGA data

width is twice the PCS data width to allow the fabric to run at half the PCS frequency.

UG-01080

2015.01.19

Rate Match FIFO

15-15

Cyclone V Transceiver Native PHY IP Core Overview

Altera Corporation

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