Altera Transceiver PHY IP Core - Manual (Page 148)

Name Value Description
Receiver static equalizer setting 0–15 This option sets the equalizer control
settings. The equalizer uses a pass band
filter. Specifying a low value passes low
frequencies. Specifying a high value
passes high frequencies. Available for
HardCopy IV and Stratix IV devices.
Advanced Options Parameters
This section describes the settings available on the Advanced Options tab.
Table 6-6: Advanced Options
Name Value Description
Include control and status ports On/Off If you turn this option on, the top-level IP core
include the status signals and digital resets
shown in XAUI Top-Level Signals—Soft PCS
and PMA and XAUI Top-Level Signals–Hard IP
PCS and PMA . If you turn this option off, you
can access control and status information using
Avalon-MM interface to the control and status
registers. The default setting is off.
External PMA control and configu‐
ration
On/Off
If you turn this option on, the PMA signals are
brought up to the top level of the XAUI IP Core.
This option is useful if your design includes
multiple instantiations of the XAUI PHY IP
Core. To save FPGA resources, you can
instantiate the Low Latency PHY Controller and
Transceiver Reconfiguration Controller IP Cores
separately in your design to avoid having these
IP cores instantiated in each instance of the
XAUI PHY IP Core. If you turn this option off,
the PMA signals remain internal to the core. The
default setting is off.
This option is available for Arria II GX,
HardCopy IV and Stratix IV devices. In these
devices, this option must be turned On to fit 2
hard XAUI instances in adjacent transceiver
quads that share the same calibration block. In
addition, the instances must share powerdown
signals.
Enable rx_recovered_clk pin On/Off When you turn this option on, the RX recovered
clock signal is an output signal.
6-8 Advanced Options Parameters
UG-01080
2015.01.19
Altera Corporation XAUI PHY IP Core
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