Altera Transceiver PHY IP Core User Manual
Page 435
Parameter
Range
Description
Enable rx_std_bitrev_ena port
On/Off
When you turn this option On, asserting
rx_
std_bitrev_ena
control port causes the RX
data order to be reversed from the normal
order, LSB to MSB, to the opposite, MSB to
LSB. This signal is an asynchronous input.
Enable rx_std_byterev_ena port
On/Off
When you turn this option On, asserting
rx_
std_byterev_ena
input control port causes
swaps the order of the individual 8- or 10-bit
words received from the PMA.
Enable tx_std_polinv port
On/Off
When you turn this option On, the
tx_std_
polinv
input is enabled. You can use this
control port to swap the positive and negative
signals of a serial differential link if they were
erroneously swapped during board layout.
Enable rx_std_polinv port
On/Off
When you turn this option On, the
rx_std_
polinv
input is enabled. You can use this
control port to swap the positive and negative
signals of a serial differential link if they were
erroneously swapped during board layout.
Enable tx_std_elecidle port
On/Off
When you turn this option On, the
tx_std_
elecidle
input port is enabled. When this
signal is asserted, it forces the transmitter to
electrical idle. This signal is required for the
PCI Express protocol.
Enable rx_std_signaldetect port
On/Off
When you turn this option On, the optional
tx_std_signaldetect
output port is
enabled. This signal is required for the PCI
Express protocol. If enabled, the signal
threshold detection circuitry senses whether
the signal level present at the RX input buffer
is above the signal detect threshold voltage
that you specified.
For SATA / SAS applications, enable this port
and set the following QSF assignments to the
transceiver receiver pin:
•
set_instance_assignment -name XCVR_
RX_SD_ENABLE ON
•
set_instance_assignment -name XCVR_
RX_SD_THRESHOLD 7
•
set_instance_assignment -name XCVR_
RX_COMMON_MODE_VOLTAGE VTT_OP55V
•
set_instance_assignment -name XCVR_
RX_SD_OFF 1
•
set_instance_assignment -name XCVR_
RX_SD_ON 2
14-24
Standard PCS Parameters for the Native PHY
UG-01080
2015.01.19
Altera Corporation
Arria V GZ Transceiver Native PHY IP Core