Altera Transceiver PHY IP Core - Manual (Page 215)

Figure 9-1: Custom PHY IP Core
Deterministic Latency PHY IP Core
Arria V, Cyclone V, or Stratix V FPGA
PCS:
Phase Comp FIFOs
Byte Serializer/
Deserializer
8B/10B
Word Aligner
Bit Slipper
PMA:
CDR
Serializer
Deserializer
TX Serial Data
RX Serial Data
to
Optical
Link
Avalon-ST TX and RX
Avalon-MM Cntrl and Status
to and from
Transceiver Reconfiguration
Controller
Related Information
• To access control and status registers in the Custom PHY, your design must include an embedded
controller with an Avalon-MM master interface
• Transceiver Configurations in Stratix V Devices
Device Family Support
IP cores provide either final or preliminary support for target Altera device families.
These terms have the following definitions:
• Final support—Verified with final timing models for this device.
• Preliminary support—Verified with preliminary timing models for this device.
Table 9-1: Device Family Support
Device Family Support
Arria V devices-Hard PCS and PMA Final
Cyclone V devices-Hard PCS and PMA Final
Stratix V devices-Hard PCS and PMA Final
Other device families No support
Performance and Resource Utilization
Because the PCS and PMA are both implemented in hard logic, the Custom PHY IP Core requires less
than 1% of FPGA resources.
9-2 Device Family Support
UG-01080
2015.01.19
Altera Corporation Custom PHY IP Core
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