Altera Transceiver PHY IP Core User Manual
Page 316
Table 12-14: 8B/10B Encoder and Decoder Parameters
Parameter
Range
Description
Enable TX 8B/10B encoder
On/Off
When you turn this option On, the PCS
includes the 8B/10B encoder.
Enable TX 8B/10B disparity control
On/Off
When you turn this option On, the PCS
includes disparity control for the 8B/10B
encoder. Your force the disparity of the 8B/
10B encoder using the
tx_forcedisp
control
signal.
Enable RX 8B/10B decoder
On/Off
When you turn this option On, the PCS
includes the 8B/10B decoder.
Rate Match FIFO
The rate match FIFO compensates for the very small frequency differences between the local system clock
and the RX recovered clock. The following table describes the rate match FIFO parameters.
Table 12-15: Rate Match FIFO Parameters
Parameter
Range
Description
Enable RX rate match FIFO
On/Off
When you turn this option On , the PCS
includes a FIFO to compensate for the very
small frequency differences between the local
system clock and the RX recovered clock.
RX rate match insert/delete +ve
pattern (hex)
User-specified
20 bit pattern
Specifies the +ve (positive) disparity value for
the RX rate match FIFO as a hexadecimal
string.
RX rate match insert/delete -ve pattern
(hex)
User-specified
20 bit pattern
Specifies the -ve (negative) disparity value for
the RX rate match FIFO as a hexadecimal
string.
Enable rx_std_rm_fifo_empty port
On/Off
When you turn this option On, the rate
match FIFO outputs a FIFO empty status flag.
The rate match FIFO compensates for small
clock frequency differences between the
upstream transmitter and the local receiver
clocks by inserting or removing skip (SKP)
symbols or ordered sets from the inter-packet
gap (IPG) or idle stream. This port is only
used for XAUI, GigE, and Serial RapidIO in
double width mode. In double width mode,
the FPGA data width is twice the PCS data
width to allow the fabric to run at half the
PCS frequency.
Enable rx_std_rm_fifo_full port
On/Off
When you turn this option On, the rate
match FIFO outputs a FIFO full status flag.
This port is only used for XAUI, GigE, and
Serial RapidIO in double width mode.
12-18
Standard PCS Parameters for the Native PHY
UG-01080
2015.01.19
Altera Corporation
Stratix V Transceiver Native PHY IP Core