Altera Transceiver PHY IP Core User Manual
Page 470
Figure 14-7: Arria V Native PHY 10G PCS Interfaces
Clocks
Frame
Generator
TX FIFO
RX FIFO
Block
Synchronizer
Frame
Synchronizer
Bit-Slip
Gearbox
Feature
64B/66B
BER
10G PCS Interface Ports
CRC32
tx_10g_coreclkin[<n>-1:0]
rx_10g_coreclkin[<n>-1:0]
tx_10g_clkout[<n>-1:0]
rx_10g_clkout[<n>-1:0]
rx_10g_clk33out[<n>-1:0]t
tx_10g_control[8<n>-1:0]
tx_10g_data_valid[<n>-1:0]
tx_10g_fifo_full[<n>-1:0]
tx_10g_fifo_pfull[<n>-1:0]
tx_10g_fifo_empty[<n>-1:0]
tx_10g_fifo_pempt[<n>-1:0]y
tx_10g_fifo_del[<n>-1:0]
tx_10g_fifo_insert[<n>-1:0]
rx_10g_control[10<n>-1:0]
rx_10g_fifo_rd_en[<n>-1:0]
rx_10g_data_valid[<n>-1:0]
rx_10g_fifo_full[<n>-1:0]
rx_10g_fifo_pfull[<n>-1:0]
rx_10g_fifo_empty[<n>-1:0]
rx_10g_fifo_pempty[<n>-1:0]
rx_10g_fifo_align_clr[<n>-1:0]
rx_10g_fifo_align_en[<n>-1:0]
rx_10g_align_val[<n>-1:0]
rx_10g_fifo_del[<n>-1:0]
rx_10g_fifo_insert[<n>-1:0]
rx_10g_crc32err[<n>-1:0]
tx_10g_diag_status[2<n>-1:0]
tx_10g_burst_en[<n>-1:0]
tx_10g_frame[<n>-1:0]
rx_10g_frame[<n>-1:0]
rx_10g_frame_lock[<n>-1:0]
rx_10g_pyld_ins[<n>-1:0]
rx_10g_frame_mfrm_err[<n>-1:0]
rx_10g_frame_sync_err[<n>-1:0]
rx_10g_scram_err[<n>-1:0]
rx_10g_frame_skip_ins[<n>-1:0]
rx_10g_frame_skip_err[<n>-1:0]
rx_10g_frame_diag_err[<n>-1:0]
rx_10g_frame_diag_status[2<n>-1:0]
rx_10g_blk_lock[<n>-1:0]
rx_10g_blk_sh_err[<n>-1:0]
rx_10g_bitslip[<n>-1:0]
tx_10g_bitslip[7<n>-1:0]
rx_10g_clr_errblk_count[<n>-1:0]
rx_10g_highber[<n>-1:0]
rx_10g_clr_highber_cnt[<n>-1:0]
PRBS
rx_10g_prbs_done
rx_10g_prbs_err
rx_10g_prbs_err_clr
The following table describes the signals available for the 10G PCS datapath. When you enable both the
10G and Standard datapaths, both sets of signals are included in the top-level HDL file for the Native
PHY.
Note: In the following table, the column labeled “Synchronous to tx_10_coreclkin/rx_10g_coreclkin” refers
to cases where the phase compensation FIFO is not in register mode.
Table 14-44: Name Dir Synchronous to tx_10g_coreclkin/rx_10g_coreclkin Description
Name
Dir
Synchro‐
nous to tx_
10g_
coreclkin/
rx_10g_
coreclkin
Description
Clocks
UG-01080
2015.01.19
10G PCS Interface
14-59
Arria V GZ Transceiver Native PHY IP Core
Altera Corporation