Altera Transceiver PHY IP Core User Manual
Page 524
Name
Value
Description
Transceiver Calibration Functions
Enable offset cancellation
On
When enabled, the Transceiver Reconfigura‐
tion Controller includes the offset cancellation
functionality. This option is always on. Offset
cancellation occurs automatically at power-up
and runs only once.
Enable duty cycle calibration
On/Off
For Arria V devices, when enable, DCD
calibrates for duty cycle distortion caused by
clock network skew. DCD calibration runs
once during power up. You should enable this
option for protocols running at greater than
4.9152 Gbps.
Enable PLL calibration
On/Off
When enabled, an algorithm that improves
the signal integrity of the PLLs is included in
the Transceiver Reconfiguration Controller IP
Core. This feature is only available for Stratix
V devices.
Create optional calibration status
ports
On/Off
When you turn this option On, the core
includes
tx_cal_busy
and
rx_cal_busy
ports. These signals are asserted when calibra‐
tion is active.
Analog Features
Enable Analog controls
On/Off
When enabled, TX and RX signal
conditioning features are enabled.
Enable EyeQ block
On/Off
When enabled, you can use the EyeQ, the on-
chip signal quality monitoring circuitry, to
estimate the actual eye opening at the receiver.
This feature is only available for Stratix V
devices.
Enable decision feedback equalizer
(DFE) block
On/Off
When you turn this option On, the
Transceiver Reconfiguration Controller
includes logic to perform DFE
Enable adaptive equalization
(AEQ) block
On/Off
When enabled, the Transceiver Reconfigura‐
tion Controller includes logic to perform
AEQ. This feature is only available for Stratix
V devices.
Reconfiguration Features
Enable channel/PLL reconfigura‐
tion
On/Off
When enabled, the Transceiver Reconfigura‐
tion Controller includes logic to include both
channel and PLL reconfiguration.
UG-01080
2015.01.19
General Options Parameters
16-7
Transceiver Reconfiguration Controller IP Core Overview
Altera Corporation