Altera Transceiver PHY IP Core User Manual
Page 479
Name
Dir
Synchro‐
nous to tx_
10g_
coreclkin/
rx_10g_
coreclkin
Description
rx_10g_frame_skip_err
[<n>-1:0]
Output
No
For the Interlaken protocol, asserted to indicate a
Skip Control Word error was received in a Skip
Control Word location within the metaframe.
This signal is sticky during the loss of block lock
and does not update until block lock is
re-established. This signal is pulse-stretched; you
must use a synchronizer.
rx_10g_frame_diag_
err[<n>-1:0]
Output
No
For the Interlaken protocol, asserted to indicate a
Diagnostic Control Word error was received in a
Diagnostic Control Word location within the
metaframe.
This signal is sticky during the loss of block lock
and does not update until block lock is
re-established. This signal is pulse-stretched; you
must use a synchronizer.
rx_10g_frame_diag_
status
[2<n>-1:0]
Output
No
For the Interlaken protocol, reflects the lane status
message contained in the framing layer Diagnostic
Word (bits[33:32]). This information is latched
when a valid Diagnostic Word is received in a
Diagnostic Word Metaframe location. This signal
is pulse-stretched; you must use a synchronizer.
Block Synchronizer
rx_10g_blk_lock
[<n>-1:0]
Output
No
Active-high status signal that is asserted when
block synchronizer acquires block lock. Valid for
the 10GBASE-R and Interlaken protocols, and any
basic mode that uses the lock state machine to
achieve and monitor block synchronization for
word alignment. Once the block synchronizer
acquires block lock, it takes at least 16 errors for
rx_10g_blk_lock
to be deasserted.
rx_10g_blk_sh_err
[<n>-1:0]
Output
No
Error status signal from block synchronizer
indicating an invalid synchronization header has
been received. Valid for the 10GBASE-R and
Interlaken protocols, and any legal basic mode that
uses the lock state machine to achieve and monitor
block synchronization for word alignment. Active
only after block lock is achieved. This signal is
generated by
rx_pma_clk
and is pulse-stretched by
3 clock cycles. You must use a synchronizer.
14-68
10G PCS Interface
UG-01080
2015.01.19
Altera Corporation
Arria V GZ Transceiver Native PHY IP Core