Altera Transceiver PHY IP Core - Manual (Page 601)

XCVR_RX_LINEAR_EQUALIZER_CONTROL
Pin Planner and Assignment Editor Name
Receiver Linear Equalizer Control
Description
Static control for the continuous time equalizer in the receiver buffer. The equalizer has 3 settings from 0–
2 corresponding to the increasing AC gain.
Options
0-2
Assign To
Pin - RX serial data
XCVR_RX_SD_ENABLE
Pin Planner and Assignment Editor Name
Receiver Signal Detection Unit Enable/Disable
Description
Enables or disables the receiver signal detection unit. During normal operation
NORMAL_SD_ON=FALSE
,
otherwise
POWER_DOWN_SD=TRUE
.
Used for the PCIe PIPE PHY, SATA and SAS protocols.
Options
FALSE
TRUE
Assign To
Pin - RX serial data
XCVR_RX_SD_OFF
Pin Planner and Assignment Editor Name
Receiver Cycle Count Before Signal Detect Block Declares Loss Of Signal
Description
Number of parallel cycles to wait before the signal detect block declares loss of signal. Only used for the
PCIe PIPE PHY, SATA, and SAS protocols.
Options
0–29
UG-01080
2015.01.19
XCVR_RX_LINEAR_EQUALIZER_CONTROL 19-7
Analog Parameters Set Using QSF Assignments Altera Corporation
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