Altera Transceiver PHY IP Core User Manual
Page 325
PCS-PMA Width
PRBS Patterns
PRBS Pattern Select
Word Aligner Size
Word Aligner Pattern
20-bit
PRBS 7
3’b000
3’b100
0x0000043040
PRBS 23
3’b001
3’b110
0x00007FFFFF
PRBS 15
3’b101
3’b100
0x0000007FFF
PRBS 31
3’b110
3’b110
0x007FFFFFFF
Registers and Values
The following table lists the offsets and registers for the Standard PCS pattern generator and verifier.
Note: All undefined register bits are reserved.
Table 12-22: Offsets for the Standard PCS Pattern Generator and Verifier
Offset
OffsetBits
R/W
Name
Description
0x97
[9]
R/W
PRBS TX Enable
When set to 1'b1, enables the PRBS
generator.
[8:6]
R/W
PRBS Pattern Select
Specifies the encoded PRBS pattern
defined in the previous table.
0x99 [9]
R/W
Clock Power Down TX
When set to 1'b1, powers down the
PRBS Clock in the transmitter. When
set to 1'b0, enables the PRBS
generator.
0xA0
[5]
R/W
PRBS RX Enable
When set to 1'b1, enables the PRBS
verifier in the receiver.
[4]
R/W
PRBS Error Clear
When set to 1'b1, deasserts
rx_prbs_
done
and restarts the PRBS pattern.
0xA1
[15:14]
R/W
Sync badcg
Must be set to 2'b00 to enable the
PRBS verifier.
[13]
R/W
Enable Comma Detect
Must be set to 1'b0 to enable the
PRBS verifier.
[11]
R/W
Enable Polarity
Must be set to 1'b0 to enable the
PRBS verifier.
[10:8]
R/W
Word Aligner Size
Specifies the word alignment size
using the encodings defined in the
previous table.
[7:0]
R/W
Word Aligner Pattern
[39:32]
Stores the high-order 8 bits of the
word aligner pattern as specified in
the previous table.
0xA2 [15:0]
R/W
Word Aligner Pattern
[31:16]
Stores the middle 16 bits of the word
aligner pattern as specified in the
previous table.
UG-01080
2015.01.19
Standard PCS Pattern Generators
12-27
Stratix V Transceiver Native PHY IP Core
Altera Corporation