Altera Transceiver PHY IP Core - Manual (Page 45)

Figure 3-8: Arria V GZ Clock Generation and Distribution
pll_ref_clk
644.53125 MHz
10.3125
Gbps serial
257.8125
MHz
257.8125
MHz
156.25 MHz
10GBASE-R Hard IP Transceiver Channel - Arria V GZ
TX
RX
TX PCS
40
TX PMA
10.3125
Gbps serial
RX PCS
40
RX PMA
TX PLL
8/33
fPLL
xgmii_rx_clk
rx_coreclkin
xgmii_tx_clk
64-bit data, 8-bit control
64-bit data, 8-bit control
10GBASE-R PHY Clocks for Stratix IV Devices
The
phy_mgmt_clk_reset
signal is the global reset that resets the entire PHY. A positive edge on this
signal triggers a reset.
Refer to the Reset Control and Power Down chapter in volume 2 of the Stratix IV Device Handbook for
additional information about reset sequences in Stratix IV devices.
The PCS runs at 257.8125 MHz using the
pma_rx_clock
provided by the PMA. You must provide the
PMA an input reference clock running at 644.53725 MHz to generate the 257.8125 MHz clock.
UG-01080
2015.01.19
10GBASE-R PHY Clocks for Stratix IV Devices 3-21
10GBASE-R PHY IP Core Altera Corporation
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