Altera Transceiver PHY IP Core - Manual (Page 389)

Parameter Range Description
Byte order pattern
(hex)
User-specified 8-
10 bit pattern
Specifies the search pattern for the byte ordering block.
Byte order pad
value (hex)
User–specified 8-
10 bit pattern
Specifies the pad pattern that is inserted by the byte ordering
block. This value is inserted when the byte order pattern is
recognized.
The byte ordering pattern should occupy the least significant
byte (LSB) of the parallel TX data. If the byte ordering block
identifies the programmed byte ordering pattern in the most
significant byte (MSB) of the byte-deserialized data, it inserts the
appropriate number of user-specified pad bytes to push the byte
ordering pattern to the LSB position, restoring proper byte
ordering.
Enable rx_std_
byteorder_ena port
On/Off Enables the optional
rx_std_byte_order_ena
control input
port. When this signal is asserted, the byte ordering block
initiates a byte ordering operation if the Byte ordering control
mode is set to manual. Once byte ordering has occurred, you
must deassert and reassert this signal to perform another byte
ordering operation. This signal is an synchronous input signal;
however, it must be asserted for at least 1 cycle of
rx_std_
clkout
.
Enable rx_std_
byteorder_flag port
On/Off Enables the optional
rx_std_byteorder_flag
status output
port. When asserted, indicates that the byte ordering block has
performed a byte order operation. This signal is asserted on the
clock cycle in which byte ordering occurred. This signal is
synchronous to the
rx_std_clkout
clock.
Related Information
Transceiver Architecture in Arria V Devices
Byte Serializer and Deserializer
The byte serializer and deserializer allow the PCS to operate at twice the data width of the PMA serializer.
This feature allows the PCS to run at a lower frequency and accommodate a wider range of FPGA
interface widths.
Note: For more information refer to the Byte Serializer and Byte Deserializer sections in the Transceiver
Architecture in Arria V Devices.
13-14 Byte Serializer and Deserializer
UG-01080
2015.01.19
Altera Corporation Arria V Transceiver Native PHY IP Core
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