Altera Transceiver PHY IP Core User Manual
Page 361
Name
Direction
Description
rx_10g_control
[10<n>-1:0]
Output
RX control signals for the Interlaken, 10GBASE-R, and Basic
protocols. These are synchronous to
rx_10g_coreclkin
. The
following signals are defined:
Interlaken mode:
•
[9]: Active-high synchronous status signal that indicates
when block lock and frame lock are achieved
• [8]: Active-high synchronous status signal that indicates a
synchronization header, metaframe or CRC32 error
•
[7]: Active-high synchronous status signal that indicates
the Diagnostic Word location within a metaframe
•
[6]: Active-high synchronous status signal that indicates
the SKIP Word location within a metaframe
•
[5]: Active-high synchronous status signal that indicates
the Scrambler State Word location within a metaframe
•
[4]: Active-high synchronous status signal that indicates
the Synchronization Word location within a metaframe
• [3]: Active-high synchronous status signal that indicates a
non-SKIP Word in the SKIP Word location within a
metaframe
•
[2]: Inversion signal, when asserted indicates that the
polarity of the signal has been inverted.
•
[1]: Synchronization header, a 1 indicates control word
•
[0]: Synchronization header, a 1 indicates data word
10GBASE-R mode:
• [9]: Active-high synchronous status signal indicating when
Block Lock is achieved
•
[8]: Active-high status signal that indicates a Idle/OS
deletion
•
[7]: MII control signal for
rx_data[63:56]
•
[6]: MII control signal for
rx_data[55:48]
•
[5]: MII control signal for
rx_data[47:40]
•
[4]: MII control signal for
rx_data[39:32]
•
[3]: MII control signal for
rx_data[31:24
]
•
[2]: MII control signal for
rx_data[23:16]
•
[1]: MII control signal for
rx_data[15:8]
•
[0]: MII control signal for
rx_data[7:0]
UG-01080
2015.01.19
10G PCS Interface
12-63
Stratix V Transceiver Native PHY IP Core
Altera Corporation