Altera Transceiver PHY IP Core User Manual
Page 568
The transceiver PHY IP cores create a separate reconfiguration interface for each channel and each TX
PLL. Each transceiver PHY IP core reports the number of reconfiguration interfaces it requires in the
message pane of its GUI. You must take note of this number so that you can enter it as a parameter in the
Transceiver Reconfiguration Controller.
The following figure shows the Low Latency PHY IP ore GUI specifying 32 channels. The message pane
indicates that reconfiguration interfaces 0–31 are for the transceiver channels and reconfiguration
interfaces 32–63 are for the TX PLLs.
Figure 16-9: Low Latency Transceiver PHY Example
Note: After Quartus II compilation, many of the interfaces are merged.
The following figure illustrates the GUI for the Transceiver Reconfiguration Controller. To connect the
Low Latency PHY IP Core instance to the Transceiver Reconfiguration Controller, you would enter 64 for
Number of reconfiguration interfaces. You would not need to enter any values for the Optional
interface grouping parameter because all of the interfaces belong to the same transceiver PHY IP core
instance.
UG-01080
2015.01.19
Understanding Logical Channel Numbering
16-51
Transceiver Reconfiguration Controller IP Core Overview
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