Altera Transceiver PHY IP Core - Manual (Page 208)

Word Addr Bits R/W Register Name Description
0x083
[31:6] RW Reserved —
[5:1] RW
tx_bitslipboundary_select Sets the number of bits the TX block needs
to slip the output. Used for very latency
sensitive protocols.
From block: TX bit-slipper.
0x084 [31:1] RW Reserved —
0x085
[31:4] RW Reserved —
[3] RW
rx_bitslip When set, the word alignment logic
operates in bitslip mode. Every time this
register transitions from 0 to 1, the RX data
slips a single bit.
From block: Word aligner.
[2] RW
rx_bytereversal_enable When set, enables byte reversal on the RX
interface.
From block: Word aligner.
[1] RW
rx_bitreversal_enable When set, enables bit reversal on the RX
interface.
From blockk: Word aligner.
[0] RW
rx_enapatternalign When set, the word alignment logic
operates in pattern detect mode.
From block: Word aligner.
8-20 PHY for PCIe (PIPE) Register Interface and Register Descriptions
UG-01080
2015.01.19
Altera Corporation PHY IP Core for PCI Express (PIPE)
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