Altera Transceiver PHY IP Core User Manual
Page 667
Chapter
Document
Version
Changes Made
Backplane Ethernet
10GBASE-KR PHY
2.6
Made the following changes:
• Corrected an error in the description of
pcs_mode_rc[5:0]
in
Table 4-17: Dynamic Reconfiguration Interface Signals. Added
back the option for GigE data mode and 10G data mode with
FEC.
• Updated the descriptions of
tx_cal_busy
and
rx_cal_busy
interface signals.
• Updated the descriptions of
tm_in_trigger[3:0]
and
tm_out_
trigger [3:0]
signals in Table 4-14: Control and Status Signals.
• Updated the descriptions of
xgmii_tx_clk
and
xgmii_rx_clk
signals in Table 4-11: XGMII and GMII Signals.
• Updated the description of
en_lcl_rxeq
and
rxeq_done
signals
in Table 4-17: Dynamic Reconfiguration Interface Signals.
• Added a note about performing read-modify-writes for all
registers in 10GBASE-KR PHY Register Definitions section.
• Added a clarification about reset sequencer in the 10GBASE-KR
PHY Clock and Reset Interfaces section on page 4-18.
• Updated
tx_clkout_1g
,
rx_clkout_1g
,
tx_coreclkin_1g
, and
rx_coreclkin_1g
connections in Figure 4-11: Clocks for
Standard and 10G PCS and TX PLLs.
UG-01080
2015.01.19
Revision History for Previous Releases of the Transceiver PHY IP Core
21-7
Additional Information for the Transceiver PHY IP Core
Altera Corporation