Altera Transceiver PHY IP Core User Manual
Page 514
Name
Dir
Synchronous to
tx_std_coreclkin/
rx_std_coreclkin
Description
tx_std_polinv[<n>-1:0]
Input
No
Polarity inversion, part of 8B10B encoder,
When set, the TX interface inverts the
polarity of the TX data.
Rate Match FIFO
rx_std_rmfifo_empty[<n>-
1:0]
Output
No
Rate match FIFO empty flag. When
asserted, the rate match FIFO is empty.
rx_std_rmfifo_full[<n>-
1:0]
Output
No
Rate match FIFO full flag. When asserted
the rate match FIFO is full. You must
synchronize this signal.
Word Aligner
rx_std_bitrev_ena[<n>-
1:0]
Input
No
When asserted, enables bit reversal on the
RX interface. Bit order may be reversed if
external transmission circuitry transmits
the most significant bit first. When
enabled, the receive circuitry receives all
words in the reverse order. The bit reversal
circuitry operates on the output of the
word aligner.
tx_std_bitslipboundar-
ysel[5<n>-1:0]
Input
No
BitSlip boundary selection signal. Specifies
the number of bits that the TX bit slipper
must slip.
rx_std_bitslipboundar-
ysel[5<n>-1:0]
Output
No
This signal operates when the word aligner
is in bitslip word alignment mode. It
reports the number of bits that the RX
block slipped to achieve deterministic
latency.
rx_std_runlength_err[<n>-
1:0]
Output
No
When asserted, indicates a run length
violation. Asserted if the number of
consecutive 1s or 0s exceeds the number
specified in the parameter editor GUI.
UG-01080
2015.01.19
Cyclone V Standard PCS Interface Ports
15-31
Cyclone V Transceiver Native PHY IP Core Overview
Altera Corporation