Altera Transceiver PHY IP Core User Manual
Page 122
Signal Name
Direction
Description
rx_hi_ber
Output
Asserted by the BER monitor block to indicate a
Sync Header high bit error rate greater than 10
-4
.
pll_locked
Output
When asserted, indicates the TX PLL is locked.
rx_is_lockedtodata
Output
When asserted, indicates the RX channel is locked
to input data.
tx_cal_busy
Output
When asserted, indicates that the initial TX calibra‐
tion is in progress. It is also asserted if reconfigura‐
tion controller is reset. It will not be asserted if you
manually re-trigger the calibration IP. You must
hold the channel in reset until calibration
completes.
rx_cal_busy
Output
When asserted, indicates that the initial RX calibra‐
tion is in progress. It is also asserted if reconfigura‐
tion controller is reset. It will not be asserted if you
manually re-trigger the calibration IP.
calc_clk_1g
Input
This clock is used for calculating the latency of the
soft 1G PCS block. This clock is only required for
when you enable 1588 in 1G mode.
rx_sync_status
Output
When asserted, indicates the word aligner has
aligned to in incoming word alignment pattern.
tx_pcfifo_error_1g
Output
When asserted, indicates that the Standard PCS TX
phase compensation FIFO is full.
rx_pcfifo_error_1g
Output
When asserted, indicates that the Standard PCS RX
phase compensation FIFO is full.
lcl_rf
Input
When asserted, indicates a Remote Fault (RF).The
MAC sends this fault signal to its link partner. Bit
D13 of the
Auto Negotiation Advanced Remote
Fault
register (0xC2) records this error.
tm_in_trigger[3:0]
Input
This is an optional signal that can be used for
hardware testing by using an oscilloscope or logic
analyzer to trigger events. If unused, tie this signal
to 1'b0.
tm_out_trigger[3:0]
Output
This is an optional signal that can be used for
hardware testing by using an oscilloscope or logic
analyzer to trigger events. You can ignore this signal
if not used.
rx_rlv
Output
When asserted, indicates a run length violation.
rx_clkslip
Input
When you turn this signal on, the deserializer skips
one serial bit or the serial clock is paused for one
cycle to achieve word alignment. As a result, the
period of the parallel clock can be extended by 1
unit interval (UI). This is an optional control input
signal.
UG-01080
2015.01.19
1G/10GbE Control and Status Interfaces
5-13
1G/10 Gbps Ethernet PHY IP Core
Altera Corporation