Altera Transceiver PHY IP Core - Manual (Page 139)

Simulation Support
The 1G/10GbE and 10GBASE-KR PHY IP core supports the following Altera-supported simulators for
this Quartus II software release:
• ModelSim Verilog
• ModelSim VHDL
• VCS Verilog
• VCS VHDL
Stratix
® V devices also support NCSIM Verilog and NCSIM VHDL simulation. When you generate a 1G/
10GbE or 10GBASE-KR PHY IP core, the Quartus II software optionally generates an IP functional
simulation model.
TimeQuest Timing Constraints
To pass timing analysis, you must decouple the clocks in different time domains. The necessary Synopsys
Design Constraints File (.sdc) timing constraints for the are included in the top-level wrapper file.
Acronyms
This table defines some commonly used Ethernet acronyms.
Table 5-18: Ethernet Acronyms
Acronym Definition
AN Auto-Negotiation in Ethernet as described in Clause 73 of IEEE 802.3ap-2007.
BER Bit Error Rate.
DME Differential Manchester Encoding.
FEC Forward error correction.
GMII Gigabit Media Independent Interface.
KR Short hand notation for Backplane Ethernet with 64b/66b encoding.
LD Local Device.
LT Link training in backplane Ethernet Clause 72 for 10GBASE-KR and
40GBASE-KR4.
LP Link partner, to which the LD is connected.
MAC Media Access Control.
MII Media independent interface.
OSI Open System Interconnection.
PCS Physical Coding Sublayer.
PHY Physical Layer in OSI 7-layer architecture, also in Altera device scope is: PCS
+ PMA.
5-30 Simulation Support
UG-01080
2015.01.19
Altera Corporation 1G/10 Gbps Ethernet PHY IP Core
Send Feedback