Protocol-specific transceiver phys, Protocol-specific transceiver phys -1 – Altera Transceiver PHY IP Core User Manual
Page 12
Introduction to the Protocol-Specific and
Native Transceiver PHYs
1
2015.01.19
UG-01080
The Arria V, Cyclone V, and Stratix V support three types of transceiver PHY implementations or
customization.
The three types of transceiver PHY implementations are the following:
• Protocol-specific PHY
• Non-protocol-specific PHY
• Native transceiver PHY
The protocol-specific transceiver PHYs configure the PMA and PCS to implement a specific protocol. In
contrast, the native PHY provides broad access to the low-level hardware, allowing you to configure the
transceiver to meet your design requirements. Examples of protocol-specific PHYs include XAUI and
Interlaken.
You must also include the reconfiguration and reset controllers when you implement a transceiver PHY
in your design.
Protocol-Specific Transceiver PHYs
The protocol-specific transceiver PHYs configure many PCS to meet the requirements of a specific
protocol, leaving fewer parameters for you to specify.
Altera offers the following protocol-specific transceiver PHYS:
• 1G/10 Gbps Ethernet
• 10GBASE-R
• Backplane Ethernet 10GBASE-KR PHY
• Interlaken
• PHY IP Core for PCI Express (PIPE)
• XAUI
These transceiver PHYs include an Avalon
®
Memory-Mapped (Avalon-MM) interface to access control
and status registers and an Avalon Streaming (Avalon-ST) interface to connect to the MAC for data
transfer.
The following figure illustrates the top level modules that comprise the protocol-specific transceiver PHY
IP cores. As illustrated, the Altera Transceiver Reconfiguration Controller IP Core is instantiated
separately.
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