Altera Transceiver PHY IP Core User Manual
Page 400
Name
Direction
Description
tx_analogreset[<n>-1:0]
Input
When asserted, resets for TX PMA, TX
clock generation block, and serializer.
Active high, edge sensitive reset signal.
Note: For Arria V devices, while
compiling a multi-channel
transceiver design, you will
see a compile warning
(12020) in Quartus II
software related to the signal
width of tx_analogreset. You
can safely ignore this
warning. Also, per-channel
TX analog reset is not
supported in Quartus II
software. Channel 0 TX
analog resets all the
transceiver channels.
tx_digitalreset[<n>-1:0]
Input
When asserted, resets the digital
components of the TX datapath. Active
high, edge sensitive, asynchronous reset
signal. If your design includes bonded
TX PCS channels, refer to Timing
Constraints for Reset Signals when Using
Bonded PCS Channels for a SDC
constraint you must include in your
design.
rx_analogreset[<n>-1:0]
Input
When asserted, resets the RX CDR,
deserializer. Active high, edge sensitive,
asynchronous reset signal.
rx_digitalreset[<n>-1:0]
Input
When asserted, resets the digital
components of the RX datapath. Active
high, edge sensitive, asynchronous reset
signal.
Parallel data ports
tx_pma_parallel_data[79:0]
Input
TX parallel data for the PMA Direct
datapath. Driven directly from the FPGA
fabric to the PMA. Not used when you
enable the Standard PCS datapath.
rx_pma_parallel_data[79:0]
Output
RX PMA parallel data driven from the
PMA to the FPGA fabric. Not used when
you enable the Standard PCS datapath.
UG-01080
2015.01.19
Common Interface Ports
13-25
Arria V Transceiver Native PHY IP Core
Altera Corporation