Altera Transceiver PHY IP Core - Manual (Page 172)

Parameter Value Description
Base data rate
1 × Lane rate
2 × Lane rate
3 × Lane rate
This option allows you to specify a Base data rate to
minimize the number of PLLs required to generate
the clocks necessary for data transmission at
different frequencies. Depending on the Lane rate
you specify, the default Base data rate can be either
1, 2, or 4 times the Lane rate; however, you can
change this value. The default value specified is for
backwards compatibility with earlier Quartus II
software releases.
Interlaken PHY Optional Port Parameters
This section describes the Interlaken PHY optional port parameters you can set on the Optional Ports
tab.
Table 7-3: Optional Ports
Parameter Value Description
Enable RX status signals,
(word lock, sync lock,
crc32 error) as part of rx_
parallel_data
On/Off When you turn this option on,
rx_parallel_
data[71:69]
are included in the top-level module.
These optional signals report the status of word and
synchronization locks and CRC32 errors. Refer to
Avalon-ST RX Signals for more information.
Create tx_coreclkin port On/Off
The
tx_coreclkin
drives the write side of TX FIFO.
This clock is required for multi-lane synchroniza‐
tion but is optional for single lane Interlaken links.
If
tx_coreclkin
is deselected for single lane
Interlaken links,
tx_user_clkout
drives the TX
side of the write FIFO. You must use the
tx_user_
clkout
output port to drive transmit data in the
Interlaken MAC.
Create rx_coreclkin port On/Off When selected
rx_coreclkin
is available as input
port which drives the read side of RX FIFO, When
deselected
rx_user_clkout
,
rx_clkout
for all
bonded receiver lanes, is routed internally to drive
the RX read side of FIFO.
rx_user_clkout
is also
available as an output port for the Interlaken MAC.
Interlaken PHY Analog Parameters
This section describes the Interlaken PHY analog parameters.
UG-01080
2015.01.19
Interlaken PHY Optional Port Parameters 7-5
Interlaken PHY IP Core Altera Corporation
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