Arria v gz transceiver native phy ip core, Arria v gz transceiver native phy ip core -1 – Altera Transceiver PHY IP Core User Manual
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Arria V GZ Transceiver Native PHY IP Core
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2015.01.19
UG-01080
Unlike other PHY IP Cores, the Native PHY IP Core does not include an Avalon Memory-Mapped
(Avalon-MM) interface. Instead, it exposes all signals directly as ports. The Arria V GZ Transceiver
Native PHY IP Core provides the following three datapaths:
• Standard PCS
• 10G PCS
• PMA Direct
You can enable the Standard PCS, the 10G PCS, or both if your design uses the Transceiver Reconfigura‐
tion Controller to change dynamically between the two PCS datapaths. The transceiver PHY does not
include an embedded reset controller. You can either design custom reset logic or incorporate Altera’s
“Transceiver PHY Reset Controller IP Core” to implement reset functionality.
In PMA Direct mode, the Native PHY provides direct access to the PMA from the FPGA fabric;
consequently, the latency for transmitted and received data is very low. However, you must implement
any PCS function that your design requires in the FPGA fabric.
The following figure illustrates the use of the Arria V GZ Transceiver Native PHY IP Core. As this figure
illustrates, TX PLL and clock data recovery (CDR) reference clocks from the pins of the device are input
to the PLL module and CDR logic. When enabled, the 10G or Standard PCS drives TX parallel data and
receives RX parallel data. When neither PCS is enabled the Native PHY operates in PMA Direct mode.
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