Altera Transceiver PHY IP Core - Manual (Page 566)

write_32 0x3A 0x6 //write the control and status register
//with a value of 0x6 to address 0x3A to initiate a read
read_32 0x3C //Read the value at address 0x3C
RMW {3’b10-,{read_32 0x3C}} //Perform a read-modify-write
//with the generator or bits and the value read from above
write_32 0x3C 0x<result from above > //Write the new value
//from above to the data register at address 0x3C
write_32 0x3A 0x5 //Write the control and status register
//with a value of 0x5 to address 0x3A
//Assert the channel resets
Enable the Square Wave Generator
//Enable the square wave generator with 5 consecutive 1s and 0s
//Generator selection and setup
read_32 0x3A //Read the control and status register
//busy bit[8] until it is clear
write_32 0x38 0x0 //write logical channel to 0x38
write_32 0x3A 0x4 //set the MIF mode 1 to address 0x3A
write_32 0x3B 0x135 //write the pattern type offset
write_32 0x3A 0x6 //write the control and status register
//with a value of 0x6 to address 0x3A to initiate a read
read_32 0x3C //Read the value at address 0x3C
RMW {16’b0101-0-0-0-00-10, {read_32 0x3C}} //Perform a
//read-modify-write with the generator or bits
//and the value read from above
write_32 0x3C 0x<result from above > //Write the new value from
//above to the data register at address 0x3C
write_32 0x3A 0x5 //Write the control and status register
// with a value of 0x5 to address 0x3A
//Generator clock setup
read_32 0x3A //Read the control and status register
//busy bit[8] until it is clear
write_32 0x38 0x0 //write logical channel to 0x38
write_32 0x3A 0x4 //set the MIF mode 1 to address 0x3A
write_32 0x3B 0x137 //write the pattern type offset
write_32 0x3A 0x6 //write the control and status register with
// a value of 0x6 to address 0x3A to initiate a read
read_32 0x3C //Read the value at address 0x3C
RMW {3’b01-, {read_32 0x3C}} //Perform a read-modified-write
//with the generator or bits and the value read from above
write_32 0x3C 0x<result from above > //Write the new value
//from above to the data register at address 0x3C
write_32 0x3A 0x5 //Write the control and status register
//with a value of 0x5 to address 0x3A
//Assert the channel resets
Enable the Pseudo-Random Generator
//Enable the pseudo-random pattern generator
//Seed A is set to 0x5. Use 2 local faults
read_32 0x3A //Read the control and status register busy
// bit[8] until it is clear
write_32 0x38 0x0 //write logical channel to 0x38
write_32 0x3A 0x4 //set the MIF mode 1 to address 0x3A
write_32 0x3B 0x12D //write the pattern type offset
write_32 0x3C 0x5 //Write the new value from above
//to the data register at address 0x3C
write_32 0x3A 0x5 //Write the control and status register
//with a value of 0x5 to address 0x3A
UG-01080
2015.01.19
Enabling the 10G PCS PRBS Generator or Verifier Using Streamer-Based
Reconfiguration
16-49
Transceiver Reconfiguration Controller IP Core Overview Altera Corporation
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