Altera Transceiver PHY IP Core - Manual (Page 162)

Word Addr Bits R/W Register Name Description
0x084
[31:16] - Reserved -
[15:8]
R
patterndetect[7:0] When asserted, indicates that the
programmed word alignment pattern has
been detected in the current word boundary.
The RX pattern detect signal is 2 bits wide
per channel or 8 bits per XAUI link. Reading
the value of the
patterndetect
registers
clears the bits.This register is only available
in the hard XAUI implementation.
From block: Word aligner.
[7:0]
syncstatus[7:0] Records the synchronization status of the
corresponding bit. The RX sync status
register has 2 bits per channel for a total of 8
bits per hard XAUI link. The RX sync status
register has 1 bit per channel for a total of 4
bits per soft XAUI link; soft XAUI uses bits
0–3. Reading the value of the
syncstatus
register clears the bits.
From block: Word aligner.
0x085
[31:16] - Reserved -
[15:8]
R
errdetect[7:0] When set, indicates that a received 10-bit
code group has an 8B/10B code violation or
disparity error. It is used along with
disperr
to differentiate between a code violation
error, a disparity error, or both. There are 2
bits per RX channel for a total of 8 bits per
XAUI link. Reading the value of the
errdetect
register clears the bits.
From block: 8B/10B decoder.
[7:0]
disperr[7:0] Indicates that the received 10-bit code or
data group has a disparity error. When set,
the corresponding
errdetect
bits are also
set. There are 2 bits per RX channel for a
total of 8 bits per XAUI link. Reading the
value of the
errdetect
register clears the
bits
From block: 8B/10B decoder.
6-22 XAUI PHY Register Interface and Register Descriptions
UG-01080
2015.01.19
Altera Corporation XAUI PHY IP Core
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