Altera Transceiver PHY IP Core - Manual (Page 628)

XCVR_TX_VOD_PRE_EMP_CTRL_SRC
Pin Planner and Assignment Editor Name
Transmitter V
OD
Pre-emphasis Control Source
Description
When set to
DYNAMIC_CTL
, the PCS block controls the V
OD
and pre-emphasis coefficients for PCI
Express. When this assignment is set to
RAM_CTL
the V
OD
and pre-emphasis are controlled by other
assignments, such as
XCVR_TX_PRE_EMP_1ST_POST_TAP
.
Options
• DYNAMIC_CTL: for PCI Express
• RAM_CTL: for all other protocols
Assign To
Pin - TX serial data
Analog Settings for Stratix V Devices
Analog PCB Settings for Stratix V Devices
This section lists the analog parameters for Stratix V devices whose original values are place holders for the
values that match your electrical board specification. The default value of an analog parameter is shown in
bold type. The parameters are listed in alphabetical order.
Related Information
• PCI Express Card Electromechanical Specification Rev. 2.0
• Stratix V Device Datasheet
• About the Pin Planner
• About the Assignment Editor
• Quartus II Settings File Manual
XCVR_GT_IO_PIN_TERMINATION
Pin Planner and Assignment Editor Name
GT Transceiver I/O Pin Termination
Description
Fine tunes the target 100-ohm on-chip termination for the specified transceiver pin. This parameter is
only for GT transceivers. It is available for both TX and RX pins.
19-34 XCVR_TX_VOD_PRE_EMP_CTRL_SRC
UG-01080
2015.01.19
Altera Corporation Analog Parameters Set Using QSF Assignments
Send Feedback